`timescale 1ns/1ps

module tb_mul_const();

    // -------------------------------------------------------------------------
    // Parameters
    // -------------------------------------------------------------------------
    localparam integer W = 16;
    localparam integer C = 16'sh0B3B;   // alpha_q15 ≈ 0.08774
    localparam signed [W-1:0] C_S = C[W-1:0];

    // -------------------------------------------------------------------------
    // DUT I/O
    // -------------------------------------------------------------------------
    reg  signed [W-1:0]     x;
    wire signed [(2*W)-1:0] y;

    // Instantiate DUT
    mul_const_shiftadd #(
        .W(W),
        .C(C)
    ) dut (
        .x(x),
        .y(y)
    );

    // -------------------------------------------------------------------------
    // Reference and verification
    // -------------------------------------------------------------------------
    reg signed [(2*W)-1:0] expected;
    integer i;
    integer errors;

    initial begin
        $display("------------------------------------------------------");
        $display(" Testbench: mul_const_shiftadd");
        $display(" W = %0d, C = %0d (0x%0h)", W, $signed(C_S), C_S);
        $display("------------------------------------------------------");

        errors = 0;

        // Exhaustively test all 16-bit signed values
        for (i = -(1<<(W-1)); i < (1<<(W-1)); i = i + 1) begin
            x = i;
            #1; // let combinational logic settle

            expected = $signed(x) * $signed(C_S);

            if (y !== expected) begin
                $display("FAIL: x=%6d (0x%04h) * C=%6d -> y=%10d (0x%08h), expected=%10d (0x%08h)",
                         $signed(x), x, $signed(C_S),
                         $signed(y), y, $signed(expected), expected);
                errors = errors + 1;
                // Uncomment next line if you want to stop on first mismatch
                // $stop;
            end

            // progress message every 4096 iterations
            if (((i + (1<<(W-1))) % 4096) == 0)
                $display("Progress: %5d / %5d values tested...",
                         i + (1<<(W-1)), (1<<W));
        end

        if (errors == 0)
            $display("✅ PASS: All %0d test cases matched perfectly.", (1<<W));
        else
            $display("❌ FAIL: %0d mismatches found out of %0d cases.",
                     errors, (1<<W));

        $finish;
    end
endmodule