`timescale 1ns/1ps

// =============================================================================
// Sigma-Delta sampler
// Samples A>B at clk
// =============================================================================
module sigmadelta_sampler(
    input wire clk,
    input wire a,
    input wire b,
    output wire o
);

    wire comp_out;
    lvds_comparator comp (
        .a(a), .b(b), .o(comp_out)
    );

    reg registered_comp_out;
    always @(posedge clk) registered_comp_out <= o;
    assign o = registered_comp_out;

endmodule