`default_nettype none

module wb_gpio_banks #(
  parameter integer NUM_BANKS = 4,
  parameter [31:0] BASE_ADDR = 32'h8000_0000
) (
  input  wire                     i_wb_clk,
  input  wire                     i_wb_rst,
  input  wire [31:0]              i_wb_adr,
  input  wire [31:0]              i_wb_dat,
  input  wire [3:0]               i_wb_sel,
  input  wire                     i_wb_we,
  input  wire                     i_wb_stb,
  input  wire [NUM_BANKS*32-1:0]  i_gpio,
  output reg  [31:0]              o_wb_rdt,
  output reg                      o_wb_ack,
  output wire [NUM_BANKS*32-1:0]  o_gpio
);

  wire [NUM_BANKS-1:0]           bank_sel;
  wire [NUM_BANKS-1:0]           bank_stb;
  wire [NUM_BANKS*32-1:0]        bank_rdt;
  wire [NUM_BANKS-1:0]           bank_ack;

  genvar gi;
  generate
    for (gi = 0; gi < NUM_BANKS; gi = gi + 1) begin : gen_gpio
      localparam [31:0] BANK_ADDR = BASE_ADDR + (gi * 4);

      assign bank_sel[gi] = (i_wb_adr == BANK_ADDR);
      assign bank_stb[gi] = i_wb_stb & bank_sel[gi];

      wb_gpio #(
        .address(BANK_ADDR)
      ) u_gpio (
        .i_wb_clk(i_wb_clk),
        .i_wb_rst(i_wb_rst),
        .i_wb_adr(i_wb_adr),
        .i_wb_dat(i_wb_dat),
        .i_wb_sel(i_wb_sel),
        .i_wb_we(i_wb_we),
        .i_wb_stb(bank_stb[gi]),
        .i_gpio(i_gpio[gi*32 +: 32]),
        .o_wb_rdt(bank_rdt[gi*32 +: 32]),
        .o_wb_ack(bank_ack[gi]),
        .o_gpio(o_gpio[gi*32 +: 32])
      );
    end
  endgenerate

  integer bi;
  always @* begin
    o_wb_rdt = 32'h0000_0000;
    o_wb_ack = 1'b0;
    for (bi = 0; bi < NUM_BANKS; bi = bi + 1) begin
      if (bank_sel[bi]) begin
        o_wb_rdt = bank_rdt[bi*32 +: 32];
        o_wb_ack = bank_ack[bi];
      end
    end
  end

endmodule