`timescale 1ns/1ps

// =============================================================================
// Clock generator
// Spartan-6 DCM wrapper with parameterized input and output ratios.
// =============================================================================
module clkgen_spartan6_impl #(
    parameter integer CLK_IN_HZ = 100000000,
    parameter integer CLKFX_DIVIDE = 20,
    parameter integer CLKFX_MULTIPLY = 3,
    parameter real CLKDV_DIVIDE = 2.0
)(
    input wire clk_in,
    output wire clk_out
);
`ifdef FPGA_SPARTAN6
    localparam real CLKIN_PERIOD_NS = 1000000000.0 / CLK_IN_HZ;

    wire clkfb;
    wire clk0;
    wire clkfx;
    wire locked_unused;
    wire [7:0] status_unused;

    DCM_SP #(
        .CLKDV_DIVIDE(CLKDV_DIVIDE),
        .CLKFX_DIVIDE(CLKFX_DIVIDE),
        .CLKFX_MULTIPLY(CLKFX_MULTIPLY),
        .CLKIN_DIVIDE_BY_2("FALSE"),
        .CLKIN_PERIOD(CLKIN_PERIOD_NS),
        .CLKOUT_PHASE_SHIFT("NONE"),
        .CLK_FEEDBACK("1X"),
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
        .PHASE_SHIFT(0),
        .STARTUP_WAIT("FALSE")
    ) dcm_sp_i (
        .CLKIN(clk_in),
        .CLKFB(clkfb),
        .CLK0(clk0),
        .CLK90(),
        .CLK180(),
        .CLK270(),
        .CLK2X(),
        .CLK2X180(),
        .CLKFX(clkfx),
        .CLKFX180(),
        .CLKDV(),
        .PSCLK(1'b0),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PSDONE(),
        .LOCKED(locked_unused),
        .STATUS(status_unused),
        .RST(1'b0),
        .DSSEN(1'b0)
    );

    BUFG clkfb_buf_i (
        .I(clk0),
        .O(clkfb)
    );

    BUFG clkout_buf_i (
        .I(clkfx),
        .O(clk_out)
    );
`else
    assign clk_out = 1'b0;

    wire _unused_clk_in;
    wire _unused_clkfx_divide;
    wire _unused_clkfx_multiply;
    wire _unused_clkdv_divide;
    assign _unused_clk_in = clk_in;
    assign _unused_clkfx_divide = CLKFX_DIVIDE[0];
    assign _unused_clkfx_multiply = CLKFX_MULTIPLY[0];
    assign _unused_clkdv_divide = (CLKDV_DIVIDE != 0.0);
`endif
endmodule