module wb_gpio #(
  parameter address = 32'h00000000
)(
  input  wire        i_wb_clk,
  input  wire        i_wb_rst,   // optional; tie low if unused
  input  wire [31:0] i_wb_adr,   // optional; can ignore for single-reg
  input  wire [31:0] i_wb_dat,
  input  wire [3:0]  i_wb_sel,
  input  wire        i_wb_we,
  input  wire        i_wb_stb,
  input  wire [31:0] i_gpio,

  output reg  [31:0] o_wb_rdt,
  output reg         o_wb_ack,
  output reg  [31:0] o_gpio
);

  initial o_gpio <= 32'h00000000;
  initial o_wb_rdt <= 32'h00000000;

  wire addr_check;
  assign addr_check = (i_wb_adr == address);

  // One-cycle ACK pulse per request (works even if stb stays high)
  always @(posedge i_wb_clk) begin
    if (i_wb_rst) begin
      o_wb_ack <= 1'b0;
    end else begin
      o_wb_ack <= i_wb_stb & ~o_wb_ack; // pulse while stb asserted
    end
  end

  // Read data (combinational or registered; registered here)
  always @(posedge i_wb_clk) begin
    if (i_wb_rst) begin
      o_wb_rdt <= 32'h0;
    end else if (i_wb_stb && !i_wb_we) begin
      o_wb_rdt <= i_gpio;
    end
  end

  // Write latch (update on the acknowledged cycle)
  always @(posedge i_wb_clk) begin
    if (i_wb_rst) begin
      o_gpio <= 32'h0;
    end else if (i_wb_stb && i_wb_we && addr_check && (i_wb_stb & ~o_wb_ack)) begin
      // Apply byte enables (so sb works if the master uses sel)
      if (i_wb_sel[0]) o_gpio[7:0]   <= i_wb_dat[7:0];
      if (i_wb_sel[1]) o_gpio[15:8]  <= i_wb_dat[15:8];
      if (i_wb_sel[2]) o_gpio[23:16] <= i_wb_dat[23:16];
      if (i_wb_sel[3]) o_gpio[31:24] <= i_wb_dat[31:24];
    end
  end

endmodule