[project]
name                = modem
version             = 0.1
out_dir             = out
build_dir           = build

[target.synth]
toolchain           = ISE
ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
toplevel            = top_generic
xst_opts            = -vlgincdir rtl/util
files_verilog       = rtl/util/conv.vh
                      rtl/toplevel/top_generic.v
                      rtl/core/nco_q15.v
                      rtl/core/sigmadelta_sampler.v
                      rtl/core/sigmadelta_rcmodel_q15.v
                      rtl/core/sigmadelta_input_q15.v
                      rtl/core/mul_const.v
                      rtl/core/lpf_iir_q15_k.v
                      rtl/core/decimate_by_r_q15.v
                      rtl/arch/spartan-6/lvds_comparator.v
                      rtl/arch/spartan-6/clk_gen.v
                      rtl/serv/serv_aligner.v
                      rtl/serv/serv_alu.v
                      rtl/serv/serv_bufreg.v
                      rtl/serv/serv_bufreg2.v
                      rtl/serv/serv_compdec.v
                      rtl/serv/serv_csr.v
                      rtl/serv/serv_ctrl.v
                      rtl/serv/serv_debug.v
                      rtl/serv/serv_decode.v
                      rtl/serv/serv_immdec.v
                      rtl/serv/serv_mem_if.v
                      rtl/serv/serv_rf_if.v
                      rtl/serv/serv_rf_ram_if.v
                      rtl/serv/serv_rf_ram.v
                      rtl/serv/serv_rf_top.v
                      rtl/serv/serv_state.v
                      rtl/serv/serv_synth_wrapper.v
                      rtl/serv/serv_top.v
                      rtl/serv/servile_arbiter.v
                      rtl/serv/servile_mux.v
                      rtl/serv/servile_rf_mem_if.v
                      rtl/serv/servile.v
                      rtl/serv/serving_ram.v
                      rtl/serv/serving.v
                      rtl/wb/wb_gpio.v
                      rtl/wb/wb_gpio_banks.v
                      rtl/core/soclet.v
files_con           = boards/mimas_v1/constraints.ucf
files_other         = rtl/util/rc_alpha_q15.vh
                      rtl/util/clog2.vh
                      sw/blinky/blinky.hex

[target.ip]
toolchain           = ISE_IP
ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2
files_def           = boards/mimas_v1/ip/clk_gen.xco

[target.sim]
toolchain           = iverilog
runtime             = all
toplevel            = tb_sigmadelta
ivl_opts            = -Irtl/util
files_verilog       = sim/tb/tb_nco_q15.v
                      sim/tb/tb_sigmadelta.v
                      sim/tb/tb_mul_const.v
                      rtl/core/nco_q15.v
                      rtl/core/lvds_comparator.v
                      rtl/core/sigmadelta_rcmodel_q15.v
                      rtl/core/sigmadelta_input_q15.v
                      rtl/core/mul_const.v
                      rtl/core/lpf_iir_q15_k.v
                      rtl/core/decimate_by_r_q15.v
                      sim/overrides/sigmadelta_sampler.v
                      sim/overrides/clk_gen.v
files_other         = rtl/util/conv.vh
                      rtl/util/rc_alpha_q15.vh