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Z80/build/boot.lst
2026-08-23 15:47:46 +02:00

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0000FFFF 1 STACK_TOP = 0xFFFF
2 ; At 500 kHz the CPU has about 500 T-states per millisecond.
3 ; The inner delay loop below costs about 26 T-states per taken iteration:
4 ; dec hl = 6T
5 ; ld a,h = 4T
6 ; or l = 4T
7 ; jr nz = 12T
8 ; 500 / 26 = 19.2, so 20 iterations is the nearest simple whole-number choice.
00000014 9 DELAY_LOOPS_PER_MS = 20
10
11 .globl _main
12 .globl _delay_ms
13 .globl _io_out
14 .globl _io_in
15 .globl s__DATA
16 .globl l__DATA
17 .globl s__INITIALIZER
18 .globl s__INITIALIZED
19 .globl l__INITIALIZER
20
21 .area _ITABLE (ABS)
22
00000000 23 .org 0x00
00000000 C3r00r00 [10] 24 jp init
00000008 25 .org 0x08
00000008 ED 4D [14] 26 reti
00000010 27 .org 0x10
00000010 ED 4D [14] 28 reti
00000018 29 .org 0x18
00000018 ED 4D [14] 30 reti
00000020 31 .org 0x20
00000020 ED 4D [14] 32 reti
00000028 33 .org 0x28
00000028 ED 4D [14] 34 reti
00000030 35 .org 0x30
00000030 ED 4D [14] 36 reti
00000038 37 .org 0x38
00000038 ED 4D [14] 38 reti
39
40 .area _HOME
00000000 41 init:
00000000 F3 [ 4] 42 di
00000001 31 FF FF [10] 43 ld sp, #STACK_TOP
44
00000004 CDr00r00 [17] 45 call gsinit
00000007 CDr00r00 [17] 46 call _main
47
0000000A 48 hang:
0000000A 18 FE [12] 49 jr hang
50
51 .area _GSINIT
00000000 52 gsinit:
00000000 01r00r00 [10] 53 ld bc, #l__INITIALIZER
00000003 78 [ 4] 54 ld a, b
00000004 B1 [ 4] 55 or c
00000005 28 08 [12] 56 jr z, zero_data
57
00000007 11r00r00 [10] 58 ld de, #s__INITIALIZED
0000000A 21r00r00 [10] 59 ld hl, #s__INITIALIZER
0000000D ED B0 [21] 60 ldir
61
0000000F 62 zero_data:
0000000F 01r00r00 [10] 63 ld bc, #l__DATA
00000012 78 [ 4] 64 ld a, b
00000013 B1 [ 4] 65 or c
00000014 28 0B [12] 66 jr z, gsinit_done
67
00000016 21r00r00 [10] 68 ld hl, #s__DATA
00000019 AF [ 4] 69 xor a
70
0000001A 71 clear_loop:
0000001A 77 [ 7] 72 ld (hl), a
0000001B 23 [ 6] 73 inc hl
0000001C 0B [ 6] 74 dec bc
0000001D 78 [ 4] 75 ld a, b
0000001E B1 [ 4] 76 or c
0000001F 20 F9 [12] 77 jr nz, clear_loop
78
00000021 79 gsinit_done:
80 .area _GSFINAL
00000000 C9 [10] 81 ret
82
83 .area _CODE
84 ; Write a byte to an I/O port.
85 ; Input: A = port address, L = data byte.
00000000 86 _io_out::
00000000 4F [ 4] 87 ld c, a
00000001 7D [ 4] 88 ld a, l
00000002 ED 79 [12] 89 out (c), a
00000004 C9 [10] 90 ret
91
92 ; Read a byte from an I/O port.
93 ; Input: A = port address.
94 ; Return: A = data byte.
00000005 95 _io_in::
00000005 4F [ 4] 96 ld c, a
00000006 ED 78 [12] 97 in a, (c)
00000008 C9 [10] 98 ret
99
100 ; Approximate millisecond delay.
101 ; Input: HL = delay in milliseconds.
102 ; For CLK_SPEED = 500000 Hz this uses 20 inner iterations per ms.
00000009 103 _delay_ms::
00000009 7C [ 4] 104 ld a, h
0000000A B5 [ 4] 105 or l
0000000B C8 [11] 106 ret z
0000000C 107 delay_ms_outer$:
0000000C E5 [11] 108 push hl
0000000D 21 14 00 [10] 109 ld hl, #DELAY_LOOPS_PER_MS
00000010 110 delay_ms_inner$:
00000010 2B [ 6] 111 dec hl
00000011 7C [ 4] 112 ld a, h
00000012 B5 [ 4] 113 or l
00000013 20 FB [12] 114 jr nz, delay_ms_inner$
00000015 E1 [10] 115 pop hl
00000016 2B [ 6] 116 dec hl
00000017 7C [ 4] 117 ld a, h
00000018 B5 [ 4] 118 or l
00000019 20 F1 [12] 119 jr nz, delay_ms_outer$
0000001B C9 [10] 120 ret