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This commit is contained in:
Joppe Blondel
2026-08-23 15:47:46 +02:00
commit 11c508bc24
18 changed files with 1350 additions and 0 deletions
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0
.codex Normal file
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49
Makefile Normal file
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TARGET := out
BUILD_DIR := build
AS := sdasz80
CC := sdcc
MAKEBIN := makebin
ASFLAGS := -plosgff
CCFLAGS := -mz80 --no-std-crt0
LDFLAGS := -mz80 --no-std-crt0 --code-loc 0x0080 --data-loc 0x8000
MAKEBINFLAGS := -p
ASM_SRCS := boot.asm
ASM_BUILDS := $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SRCS)))
C_SRCS := main.c
C_BUILDS := $(addprefix $(BUILD_DIR)/,$(notdir $(C_SRCS)))
ASM_RELS := $(ASM_BUILDS:.asm=.rel)
C_RELS := $(C_BUILDS:.c=.rel)
IHX := $(BUILD_DIR)/$(TARGET).ihx
MAP := $(BUILD_DIR)/$(TARGET).map
BIN := $(BUILD_DIR)/$(TARGET).bin
LST := $(ASM_BUILDS:.asm=.lst)
SYM := $(ASM_BUILDS:.asm=.sym)
GENERATED := $(ASM_BUILDS) $(C_BUILDS) $(ASM_RELS) $(C_RELS) $(LST) $(SYM) $(IHX) $(MAP) $(BIN)
.PHONY: all clean
all: $(BIN)
$(BIN): $(IHX)
$(MAKEBIN) $(MAKEBINFLAGS) $< $@
$(IHX): $(ASM_RELS) $(C_RELS) | $(BUILD_DIR)
$(CC) $(LDFLAGS) -o $@ $(ASM_RELS) $(C_RELS)
$(BUILD_DIR)/%.rel: %.asm | $(BUILD_DIR)
$(AS) $(ASFLAGS) -o $@ $<
$(BUILD_DIR)/%.rel: %.c | $(BUILD_DIR)
$(CC) $(CCFLAGS) -c -o $@ $<
$(BUILD_DIR):
mkdir -p $@
clean:
rm -rf $(BUILD_DIR)

120
boot.asm Normal file
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STACK_TOP = 0xFFFF
; At 500 kHz the CPU has about 500 T-states per millisecond.
; The inner delay loop below costs about 26 T-states per taken iteration:
; dec hl = 6T
; ld a,h = 4T
; or l = 4T
; jr nz = 12T
; 500 / 26 = 19.2, so 20 iterations is the nearest simple whole-number choice.
DELAY_LOOPS_PER_MS = 20
.globl _main
.globl _delay_ms
.globl _io_out
.globl _io_in
.globl s__DATA
.globl l__DATA
.globl s__INITIALIZER
.globl s__INITIALIZED
.globl l__INITIALIZER
.area _ITABLE (ABS)
.org 0x00
jp init
.org 0x08
reti
.org 0x10
reti
.org 0x18
reti
.org 0x20
reti
.org 0x28
reti
.org 0x30
reti
.org 0x38
reti
.area _HOME
init:
di
ld sp, #STACK_TOP
call gsinit
call _main
hang:
jr hang
.area _GSINIT
gsinit:
ld bc, #l__INITIALIZER
ld a, b
or c
jr z, zero_data
ld de, #s__INITIALIZED
ld hl, #s__INITIALIZER
ldir
zero_data:
ld bc, #l__DATA
ld a, b
or c
jr z, gsinit_done
ld hl, #s__DATA
xor a
clear_loop:
ld (hl), a
inc hl
dec bc
ld a, b
or c
jr nz, clear_loop
gsinit_done:
.area _GSFINAL
ret
.area _CODE
; Write a byte to an I/O port.
; Input: A = port address, L = data byte.
_io_out::
ld c, a
ld a, l
out (c), a
ret
; Read a byte from an I/O port.
; Input: A = port address.
; Return: A = data byte.
_io_in::
ld c, a
in a, (c)
ret
; Approximate millisecond delay.
; Input: HL = delay in milliseconds.
; For CLK_SPEED = 500000 Hz this uses 20 inner iterations per ms.
_delay_ms::
ld a, h
or l
ret z
delay_ms_outer$:
push hl
ld hl, #DELAY_LOOPS_PER_MS
delay_ms_inner$:
dec hl
ld a, h
or l
jr nz, delay_ms_inner$
pop hl
dec hl
ld a, h
or l
jr nz, delay_ms_outer$
ret

14
boot.h Normal file
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#ifndef _BOOT_H
#define _BOOT_H
#include <stdint.h>
#define PIO_A_DATA 0x40
#define PIO_A_CTRL 0x42
void io_out(uint8_t addr, uint8_t data);
uint8_t io_in(uint8_t addr);
void delay_ms(uint16_t ms);
#endif

120
build/boot.lst Normal file
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0000FFFF 1 STACK_TOP = 0xFFFF
2 ; At 500 kHz the CPU has about 500 T-states per millisecond.
3 ; The inner delay loop below costs about 26 T-states per taken iteration:
4 ; dec hl = 6T
5 ; ld a,h = 4T
6 ; or l = 4T
7 ; jr nz = 12T
8 ; 500 / 26 = 19.2, so 20 iterations is the nearest simple whole-number choice.
00000014 9 DELAY_LOOPS_PER_MS = 20
10
11 .globl _main
12 .globl _delay_ms
13 .globl _io_out
14 .globl _io_in
15 .globl s__DATA
16 .globl l__DATA
17 .globl s__INITIALIZER
18 .globl s__INITIALIZED
19 .globl l__INITIALIZER
20
21 .area _ITABLE (ABS)
22
00000000 23 .org 0x00
00000000 C3r00r00 [10] 24 jp init
00000008 25 .org 0x08
00000008 ED 4D [14] 26 reti
00000010 27 .org 0x10
00000010 ED 4D [14] 28 reti
00000018 29 .org 0x18
00000018 ED 4D [14] 30 reti
00000020 31 .org 0x20
00000020 ED 4D [14] 32 reti
00000028 33 .org 0x28
00000028 ED 4D [14] 34 reti
00000030 35 .org 0x30
00000030 ED 4D [14] 36 reti
00000038 37 .org 0x38
00000038 ED 4D [14] 38 reti
39
40 .area _HOME
00000000 41 init:
00000000 F3 [ 4] 42 di
00000001 31 FF FF [10] 43 ld sp, #STACK_TOP
44
00000004 CDr00r00 [17] 45 call gsinit
00000007 CDr00r00 [17] 46 call _main
47
0000000A 48 hang:
0000000A 18 FE [12] 49 jr hang
50
51 .area _GSINIT
00000000 52 gsinit:
00000000 01r00r00 [10] 53 ld bc, #l__INITIALIZER
00000003 78 [ 4] 54 ld a, b
00000004 B1 [ 4] 55 or c
00000005 28 08 [12] 56 jr z, zero_data
57
00000007 11r00r00 [10] 58 ld de, #s__INITIALIZED
0000000A 21r00r00 [10] 59 ld hl, #s__INITIALIZER
0000000D ED B0 [21] 60 ldir
61
0000000F 62 zero_data:
0000000F 01r00r00 [10] 63 ld bc, #l__DATA
00000012 78 [ 4] 64 ld a, b
00000013 B1 [ 4] 65 or c
00000014 28 0B [12] 66 jr z, gsinit_done
67
00000016 21r00r00 [10] 68 ld hl, #s__DATA
00000019 AF [ 4] 69 xor a
70
0000001A 71 clear_loop:
0000001A 77 [ 7] 72 ld (hl), a
0000001B 23 [ 6] 73 inc hl
0000001C 0B [ 6] 74 dec bc
0000001D 78 [ 4] 75 ld a, b
0000001E B1 [ 4] 76 or c
0000001F 20 F9 [12] 77 jr nz, clear_loop
78
00000021 79 gsinit_done:
80 .area _GSFINAL
00000000 C9 [10] 81 ret
82
83 .area _CODE
84 ; Write a byte to an I/O port.
85 ; Input: A = port address, L = data byte.
00000000 86 _io_out::
00000000 4F [ 4] 87 ld c, a
00000001 7D [ 4] 88 ld a, l
00000002 ED 79 [12] 89 out (c), a
00000004 C9 [10] 90 ret
91
92 ; Read a byte from an I/O port.
93 ; Input: A = port address.
94 ; Return: A = data byte.
00000005 95 _io_in::
00000005 4F [ 4] 96 ld c, a
00000006 ED 78 [12] 97 in a, (c)
00000008 C9 [10] 98 ret
99
100 ; Approximate millisecond delay.
101 ; Input: HL = delay in milliseconds.
102 ; For CLK_SPEED = 500000 Hz this uses 20 inner iterations per ms.
00000009 103 _delay_ms::
00000009 7C [ 4] 104 ld a, h
0000000A B5 [ 4] 105 or l
0000000B C8 [11] 106 ret z
0000000C 107 delay_ms_outer$:
0000000C E5 [11] 108 push hl
0000000D 21 14 00 [10] 109 ld hl, #DELAY_LOOPS_PER_MS
00000010 110 delay_ms_inner$:
00000010 2B [ 6] 111 dec hl
00000011 7C [ 4] 112 ld a, h
00000012 B5 [ 4] 113 or l
00000013 20 FB [12] 114 jr nz, delay_ms_inner$
00000015 E1 [10] 115 pop hl
00000016 2B [ 6] 116 dec hl
00000017 7C [ 4] 117 ld a, h
00000018 B5 [ 4] 118 or l
00000019 20 F1 [12] 119 jr nz, delay_ms_outer$
0000001B C9 [10] 120 ret

103
build/boot.rel Normal file
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XL4
H D areas A global symbols
S l__DATA Ref00000000
S _main Ref00000000
S s__DATA Ref00000000
S .__.ABS. Def00000000
S s__INITIALIZED Ref00000000
S l__INITIALIZER Ref00000000
S s__INITIALIZER Ref00000000
A _CODE size 1C flags 0 addr 0
S _io_in Def00000005
S _delay_ms Def00000009
S _io_out Def00000000
A _ITABLE size 0 flags 8 addr 0
A _ITABLE0 size 3 flags 8 addr 0
A _ITABLE1 size 2 flags 8 addr 8
A _ITABLE2 size 2 flags 8 addr 10
A _ITABLE3 size 2 flags 8 addr 18
A _ITABLE4 size 2 flags 8 addr 20
A _ITABLE5 size 2 flags 8 addr 28
A _ITABLE6 size 2 flags 8 addr 30
A _ITABLE7 size 2 flags 8 addr 38
A _HOME size C flags 0 addr 0
A _GSINIT size 21 flags 0 addr 0
A _GSFINAL size 1 flags 0 addr 0
T 00 00 00 00
R 00 00 02 00
T 00 00 00 00 C3 00 00
R 00 00 02 00 00 05 0A 00
T 08 00 00 00
R 00 00 03 00
T 08 00 00 00 ED 4D
R 00 00 03 00
T 10 00 00 00
R 00 00 04 00
T 10 00 00 00 ED 4D
R 00 00 04 00
T 18 00 00 00
R 00 00 05 00
T 18 00 00 00 ED 4D
R 00 00 05 00
T 20 00 00 00
R 00 00 06 00
T 20 00 00 00 ED 4D
R 00 00 06 00
T 28 00 00 00
R 00 00 07 00
T 28 00 00 00 ED 4D
R 00 00 07 00
T 30 00 00 00
R 00 00 08 00
T 30 00 00 00 ED 4D
R 00 00 08 00
T 38 00 00 00
R 00 00 09 00
T 38 00 00 00 ED 4D
R 00 00 09 00
T 00 00 00 00
R 00 00 0A 00
T 00 00 00 00 F3 31 FF FF CD 00 00 CD 00 00
R 00 00 0A 00 00 09 0B 00 02 0C 01 00
T 0A 00 00 00
R 00 00 0A 00
T 0A 00 00 00 18 FE
R 00 00 0A 00
T 00 00 00 00
R 00 00 0B 00
T 00 00 00 00 01 00 00 78 B1 28 08 11 00 00 21
R 00 00 0B 00 02 05 05 00 02 0C 04 00
T 0B 00 00 00 00 00 ED B0
R 00 00 0B 00 02 04 06 00
T 0F 00 00 00
R 00 00 0B 00
T 0F 00 00 00 01 00 00 78 B1 28 0B 21 00 00 AF
R 00 00 0B 00 02 05 00 00 02 0C 02 00
T 1A 00 00 00
R 00 00 0B 00
T 1A 00 00 00 77 23 0B 78 B1 20 F9
R 00 00 0B 00
T 21 00 00 00
R 00 00 0B 00
T 00 00 00 00 C9
R 00 00 0C 00
T 00 00 00 00
R 00 00 00 00
T 00 00 00 00 4F 7D ED 79 C9
R 00 00 00 00
T 05 00 00 00
R 00 00 00 00
T 05 00 00 00 4F ED 78 C9
R 00 00 00 00
T 09 00 00 00
R 00 00 00 00
T 09 00 00 00 7C B5 C8
R 00 00 00 00
T 0C 00 00 00
R 00 00 00 00
T 0C 00 00 00 E5 21 14 00
R 00 00 00 00
T 10 00 00 00
R 00 00 00 00
T 10 00 00 00 2B 7C B5 20 FB E1 2B 7C B5 20 F1 C9
R 00 00 00 00

33
build/boot.sym Normal file
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ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next / eZ80 / R800) Page 1
Hexadecimal [32-Bits]
Symbol Table
.__.$$$.= 00002710 L | .__.ABS.= 00000000 G | .__.CPU.= 00000000 L
.__.H$L.= 00000000 L | DELAY_LO= 00000014 | STACK_TO= 0000FFFF
0 _delay_m 00000009 GR | 0 _io_in 00000005 GR | 0 _io_out 00000000 GR
_main ******** GX | B clear_lo 0000001A R | 0 delay_ms 00000010 R
0 delay_ms 0000000C R | B gsinit 00000000 R | B gsinit_d 00000021 R
A hang 0000000A R | A init 00000000 R | l__DATA ******** GX
l__INITI ******** GX | s__DATA ******** GX | s__INITI ******** GX
s__INITI ******** GX | B zero_dat 0000000F R
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next / eZ80 / R800) Page 2
Hexadecimal [32-Bits]
Area Table
0 _CODE size 1C flags 0
1 _ITABLE size 0 flags 8
2 _ITABLE0 size 3 flags 8
3 _ITABLE1 size 2 flags 8
4 _ITABLE2 size 2 flags 8
5 _ITABLE3 size 2 flags 8
6 _ITABLE4 size 2 flags 8
7 _ITABLE5 size 2 flags 8
8 _ITABLE6 size 2 flags 8
9 _ITABLE7 size 2 flags 8
A _HOME size C flags 0
B _GSINIT size 21 flags 0
C _GSFINAL size 1 flags 0

220
build/main.asm Normal file
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;--------------------------------------------------------
; File Created by SDCC : free open source ISO C Compiler
; Version 4.5.0 #15242 (Linux)
;--------------------------------------------------------
.module main
.optsdcc -mz80 sdcccall(1)
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _main
.globl _delay_ms
.globl _io_in
.globl _io_out
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area _DABS (ABS)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area _HOME
.area _GSINIT
.area _GSFINAL
.area _GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area _HOME
.area _HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area _CODE
;main.c:19: static void acia_init(void)
; ---------------------------------
; Function acia_init
; ---------------------------------
_acia_init:
;main.c:21: io_out(ACIA_CTRL_STATUS, ACIA_CMD_MASTER_RESET);
ld l, #0x03
ld a, #0x20
call _io_out
;main.c:22: io_out(ACIA_CTRL_STATUS, ACIA_CMD_8N1_DIV16);
ld l, #0x15
ld a, #0x20
;main.c:23: }
jp _io_out
;main.c:25: static uint8_t acia_status(void)
; ---------------------------------
; Function acia_status
; ---------------------------------
_acia_status:
;main.c:27: return io_in(ACIA_CTRL_STATUS);
ld a, #0x20
;main.c:28: }
jp _io_in
;main.c:30: static void acia_putc(uint8_t value)
; ---------------------------------
; Function acia_putc
; ---------------------------------
_acia_putc:
ld l, a
;main.c:32: while ((acia_status() & ACIA_STATUS_TDRE) == 0) {
00101$:
push hl
call _acia_status
pop hl
bit 1, a
jr Z, 00101$
;main.c:34: io_out(ACIA_DATA, value);
ld a, #0x21
;main.c:35: }
jp _io_out
;main.c:37: static uint8_t acia_getc_nonblocking(uint8_t *value)
; ---------------------------------
; Function acia_getc_nonblocking
; ---------------------------------
_acia_getc_nonblocking:
;main.c:39: if ((acia_status() & ACIA_STATUS_RDRF) == 0) {
push hl
call _acia_status
pop hl
rrca
jr C, 00102$
;main.c:40: return 0;
xor a, a
ret
00102$:
;main.c:43: *value = io_in(ACIA_DATA);
push hl
ld a, #0x21
call _io_in
pop hl
ld (hl), a
;main.c:44: return 1;
ld a, #0x01
;main.c:45: }
ret
;main.c:47: static void acia_puts(const char *text)
; ---------------------------------
; Function acia_puts
; ---------------------------------
_acia_puts:
;main.c:49: while (*text) {
00101$:
ld a, (hl)
or a, a
ret Z
;main.c:50: acia_putc((uint8_t)*text++);
inc hl
push hl
call _acia_putc
pop hl
;main.c:52: }
jr 00101$
;main.c:54: void main(void)
; ---------------------------------
; Function main
; ---------------------------------
_main::
push af
;main.c:57: uint8_t ch = 0;
ld iy, #0
add iy, sp
ld 0 (iy), #0x00
;main.c:59: io_out(PIO_A_CTRL, 0x0F);
ld l, #0x0f
ld a, #0x42
call _io_out
;main.c:60: io_out(PIO_A_DATA, 0x00);
ld l, #0x00
ld a, #0x40
call _io_out
;main.c:62: acia_init();
call _acia_init
;main.c:63: acia_puts("ACIA 6850 test ready\r\n");
ld hl, #___str_0
call _acia_puts
ld iy, #1
add iy, sp
ld 0 (iy), #0x00
00106$:
;main.c:66: uint8_t status = acia_status();
call _acia_status
;main.c:68: if (acia_getc_nonblocking(&ch)) {
ld hl, #0
add hl, sp
call _acia_getc_nonblocking
or a, a
jr Z, 00104$
;main.c:69: io_out(PIO_A_DATA, ch);
ld iy, #0
add iy, sp
ld l, 0 (iy)
ld a, #0x40
call _io_out
;main.c:70: acia_putc(ch);
ld hl, #0
add hl, sp
ld a, (hl)
call _acia_putc
;main.c:71: if (ch == '\r') {
ld hl, #0
add hl, sp
ld a, (hl)
sub a, #0x0d
jr NZ, 00102$
;main.c:72: acia_putc('\n');
ld a, #0x0a
call _acia_putc
00102$:
;main.c:74: delay_ms(50);
ld hl, #0x0032
call _delay_ms
00104$:
;main.c:77: acia_putc((uint8_t)('0' + (cnt & 0x07)));
ld hl, #1
add hl, sp
ld a, (hl)
and a, #0x07
add a, #0x30
call _acia_putc
;main.c:78: acia_puts("\r\n");
ld hl, #___str_1
call _acia_puts
;main.c:79: cnt++;
ld iy, #1
add iy, sp
inc 0 (iy)
;main.c:80: delay_ms(250);
ld hl, #0x00fa
call _delay_ms
jr 00106$
;main.c:82: }
pop af
ret
___str_0:
.ascii "ACIA 6850 test ready"
.db 0x0d
.db 0x0a
.db 0x00
___str_1:
.db 0x0d
.db 0x0a
.db 0x00
.area _CODE
.area _INITIALIZER
.area _CABS (ABS)

222
build/main.lst Normal file
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1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module main
6
7 .optsdcc -mz80 sdcccall(1)
8 ;--------------------------------------------------------
9 ; Public variables in this module
10 ;--------------------------------------------------------
11 .globl _main
12 .globl _delay_ms
13 .globl _io_in
14 .globl _io_out
15 ;--------------------------------------------------------
16 ; special function registers
17 ;--------------------------------------------------------
18 ;--------------------------------------------------------
19 ; ram data
20 ;--------------------------------------------------------
21 .area _DATA
22 ;--------------------------------------------------------
23 ; ram data
24 ;--------------------------------------------------------
25 .area _INITIALIZED
26 ;--------------------------------------------------------
27 ; absolute external ram data
28 ;--------------------------------------------------------
29 .area _DABS (ABS)
30 ;--------------------------------------------------------
31 ; global & static initialisations
32 ;--------------------------------------------------------
33 .area _HOME
34 .area _GSINIT
35 .area _GSFINAL
36 .area _GSINIT
37 ;--------------------------------------------------------
38 ; Home
39 ;--------------------------------------------------------
40 .area _HOME
41 .area _HOME
42 ;--------------------------------------------------------
43 ; code
44 ;--------------------------------------------------------
45 .area _CODE
46 ;main.c:19: static void acia_init(void)
47 ; ---------------------------------
48 ; Function acia_init
49 ; ---------------------------------
00000000 50 _acia_init:
51 ;main.c:21: io_out(ACIA_CTRL_STATUS, ACIA_CMD_MASTER_RESET);
00000000 2E 03 [ 7] 52 ld l, #0x03
00000002 3E 20 [ 7] 53 ld a, #0x20
00000004 CDr00r00 [17] 54 call _io_out
55 ;main.c:22: io_out(ACIA_CTRL_STATUS, ACIA_CMD_8N1_DIV16);
00000007 2E 15 [ 7] 56 ld l, #0x15
00000009 3E 20 [ 7] 57 ld a, #0x20
58 ;main.c:23: }
0000000B C3r00r00 [10] 59 jp _io_out
60 ;main.c:25: static uint8_t acia_status(void)
61 ; ---------------------------------
62 ; Function acia_status
63 ; ---------------------------------
0000000E 64 _acia_status:
65 ;main.c:27: return io_in(ACIA_CTRL_STATUS);
0000000E 3E 20 [ 7] 66 ld a, #0x20
67 ;main.c:28: }
00000010 C3r00r00 [10] 68 jp _io_in
69 ;main.c:30: static void acia_putc(uint8_t value)
70 ; ---------------------------------
71 ; Function acia_putc
72 ; ---------------------------------
00000013 73 _acia_putc:
00000013 6F [ 4] 74 ld l, a
75 ;main.c:32: while ((acia_status() & ACIA_STATUS_TDRE) == 0) {
00000014 76 00101$:
00000014 E5 [11] 77 push hl
00000015 CDr0Er00 [17] 78 call _acia_status
00000018 E1 [10] 79 pop hl
00000019 CB 4F [ 8] 80 bit 1, a
0000001B 28 F7 [12] 81 jr Z, 00101$
82 ;main.c:34: io_out(ACIA_DATA, value);
0000001D 3E 21 [ 7] 83 ld a, #0x21
84 ;main.c:35: }
0000001F C3r00r00 [10] 85 jp _io_out
86 ;main.c:37: static uint8_t acia_getc_nonblocking(uint8_t *value)
87 ; ---------------------------------
88 ; Function acia_getc_nonblocking
89 ; ---------------------------------
00000022 90 _acia_getc_nonblocking:
91 ;main.c:39: if ((acia_status() & ACIA_STATUS_RDRF) == 0) {
00000022 E5 [11] 92 push hl
00000023 CDr0Er00 [17] 93 call _acia_status
00000026 E1 [10] 94 pop hl
00000027 0F [ 4] 95 rrca
00000028 38 02 [12] 96 jr C, 00102$
97 ;main.c:40: return 0;
0000002A AF [ 4] 98 xor a, a
0000002B C9 [10] 99 ret
0000002C 100 00102$:
101 ;main.c:43: *value = io_in(ACIA_DATA);
0000002C E5 [11] 102 push hl
0000002D 3E 21 [ 7] 103 ld a, #0x21
0000002F CDr00r00 [17] 104 call _io_in
00000032 E1 [10] 105 pop hl
00000033 77 [ 7] 106 ld (hl), a
107 ;main.c:44: return 1;
00000034 3E 01 [ 7] 108 ld a, #0x01
109 ;main.c:45: }
00000036 C9 [10] 110 ret
111 ;main.c:47: static void acia_puts(const char *text)
112 ; ---------------------------------
113 ; Function acia_puts
114 ; ---------------------------------
00000037 115 _acia_puts:
116 ;main.c:49: while (*text) {
00000037 117 00101$:
00000037 7E [ 7] 118 ld a, (hl)
00000038 B7 [ 4] 119 or a, a
00000039 C8 [11] 120 ret Z
121 ;main.c:50: acia_putc((uint8_t)*text++);
0000003A 23 [ 6] 122 inc hl
0000003B E5 [11] 123 push hl
0000003C CDr13r00 [17] 124 call _acia_putc
0000003F E1 [10] 125 pop hl
126 ;main.c:52: }
00000040 18 F5 [12] 127 jr 00101$
128 ;main.c:54: void main(void)
129 ; ---------------------------------
130 ; Function main
131 ; ---------------------------------
00000042 132 _main::
00000042 F5 [11] 133 push af
134 ;main.c:57: uint8_t ch = 0;
00000043 FD 21 00 00 [14] 135 ld iy, #0
00000047 FD 39 [15] 136 add iy, sp
00000049 FD 36 00 00 [19] 137 ld 0 (iy), #0x00
138 ;main.c:59: io_out(PIO_A_CTRL, 0x0F);
0000004D 2E 0F [ 7] 139 ld l, #0x0f
0000004F 3E 42 [ 7] 140 ld a, #0x42
00000051 CDr00r00 [17] 141 call _io_out
142 ;main.c:60: io_out(PIO_A_DATA, 0x00);
00000054 2E 00 [ 7] 143 ld l, #0x00
00000056 3E 40 [ 7] 144 ld a, #0x40
00000058 CDr00r00 [17] 145 call _io_out
146 ;main.c:62: acia_init();
0000005B CDr00r00 [17] 147 call _acia_init
148 ;main.c:63: acia_puts("ACIA 6850 test ready\r\n");
0000005E 21rCAr00 [10] 149 ld hl, #___str_0
00000061 CDr37r00 [17] 150 call _acia_puts
00000064 FD 21 01 00 [14] 151 ld iy, #1
00000068 FD 39 [15] 152 add iy, sp
0000006A FD 36 00 00 [19] 153 ld 0 (iy), #0x00
0000006E 154 00106$:
155 ;main.c:66: uint8_t status = acia_status();
0000006E CDr0Er00 [17] 156 call _acia_status
157 ;main.c:68: if (acia_getc_nonblocking(&ch)) {
00000071 21 00 00 [10] 158 ld hl, #0
00000074 39 [11] 159 add hl, sp
00000075 CDr22r00 [17] 160 call _acia_getc_nonblocking
00000078 B7 [ 4] 161 or a, a
00000079 28 2A [12] 162 jr Z, 00104$
163 ;main.c:69: io_out(PIO_A_DATA, ch);
0000007B FD 21 00 00 [14] 164 ld iy, #0
0000007F FD 39 [15] 165 add iy, sp
00000081 FD 6E 00 [19] 166 ld l, 0 (iy)
00000084 3E 40 [ 7] 167 ld a, #0x40
00000086 CDr00r00 [17] 168 call _io_out
169 ;main.c:70: acia_putc(ch);
00000089 21 00 00 [10] 170 ld hl, #0
0000008C 39 [11] 171 add hl, sp
0000008D 7E [ 7] 172 ld a, (hl)
0000008E CDr13r00 [17] 173 call _acia_putc
174 ;main.c:71: if (ch == '\r') {
00000091 21 00 00 [10] 175 ld hl, #0
00000094 39 [11] 176 add hl, sp
00000095 7E [ 7] 177 ld a, (hl)
00000096 D6 0D [ 7] 178 sub a, #0x0d
00000098 20 05 [12] 179 jr NZ, 00102$
180 ;main.c:72: acia_putc('\n');
0000009A 3E 0A [ 7] 181 ld a, #0x0a
0000009C CDr13r00 [17] 182 call _acia_putc
0000009F 183 00102$:
184 ;main.c:74: delay_ms(50);
0000009F 21 32 00 [10] 185 ld hl, #0x0032
000000A2 CDr00r00 [17] 186 call _delay_ms
000000A5 187 00104$:
188 ;main.c:77: acia_putc((uint8_t)('0' + (cnt & 0x07)));
000000A5 21 01 00 [10] 189 ld hl, #1
000000A8 39 [11] 190 add hl, sp
000000A9 7E [ 7] 191 ld a, (hl)
000000AA E6 07 [ 7] 192 and a, #0x07
000000AC C6 30 [ 7] 193 add a, #0x30
000000AE CDr13r00 [17] 194 call _acia_putc
195 ;main.c:78: acia_puts("\r\n");
000000B1 21rE1r00 [10] 196 ld hl, #___str_1
000000B4 CDr37r00 [17] 197 call _acia_puts
198 ;main.c:79: cnt++;
000000B7 FD 21 01 00 [14] 199 ld iy, #1
000000BB FD 39 [15] 200 add iy, sp
000000BD FD 34 00 [23] 201 inc 0 (iy)
202 ;main.c:80: delay_ms(250);
000000C0 21 FA 00 [10] 203 ld hl, #0x00fa
000000C3 CDr00r00 [17] 204 call _delay_ms
000000C6 18 A6 [12] 205 jr 00106$
206 ;main.c:82: }
000000C8 F1 [10] 207 pop af
000000C9 C9 [10] 208 ret
000000CA 209 ___str_0:
000000CA 41 43 49 41 20 36 38 210 .ascii "ACIA 6850 test ready"
35 30 20 74 65 73 74
20 72 65 61 64 79
000000DE 0D 211 .db 0x0d
000000DF 0A 212 .db 0x0a
000000E0 00 213 .db 0x00
000000E1 214 ___str_1:
000000E1 0D 215 .db 0x0d
000000E2 0A 216 .db 0x0a
000000E3 00 217 .db 0x00
218 .area _CODE
219 .area _INITIALIZER
220 .area _CABS (ABS)

98
build/main.rel Normal file
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@@ -0,0 +1,98 @@
XL4
H 9 areas 5 global symbols
M main
O -mz80 sdcccall(1)
S .__.ABS. Def00000000
S _io_in Ref00000000
S _delay_ms Ref00000000
S _io_out Ref00000000
A _CODE size E4 flags 0 addr 0
S _main Def00000042
A _DATA size 0 flags 0 addr 0
A _INITIALIZED size 0 flags 0 addr 0
A _DABS size 0 flags 8 addr 0
A _HOME size 0 flags 0 addr 0
A _GSINIT size 0 flags 0 addr 0
A _GSFINAL size 0 flags 0 addr 0
A _INITIALIZER size 0 flags 0 addr 0
A _CABS size 0 flags 8 addr 0
T 00 00 00 00
R 00 00 00 00
T 00 00 00 00 2E 03 3E 20 CD 00 00 2E 15 3E 20 C3
R 00 00 00 00 02 09 03 00
T 0C 00 00 00 00 00
R 00 00 00 00 02 04 03 00
T 0E 00 00 00
R 00 00 00 00
T 0E 00 00 00 3E 20 C3 00 00
R 00 00 00 00 02 07 01 00
T 13 00 00 00
R 00 00 00 00
T 13 00 00 00 6F
R 00 00 00 00
T 14 00 00 00
R 00 00 00 00
T 14 00 00 00 E5 CD 0E 00 E1 CB 4F 28 F7 3E 21 C3
R 00 00 00 00 00 06 00 00
T 20 00 00 00 00 00
R 00 00 00 00 02 04 03 00
T 22 00 00 00
R 00 00 00 00
T 22 00 00 00 E5 CD 0E 00 E1 0F 38 02 AF C9
R 00 00 00 00 00 06 00 00
T 2C 00 00 00
R 00 00 00 00
T 2C 00 00 00 E5 3E 21 CD 00 00 E1 77 3E 01 C9
R 00 00 00 00 02 08 01 00
T 37 00 00 00
R 00 00 00 00
T 37 00 00 00
R 00 00 00 00
T 37 00 00 00 7E B7 C8 23 E5 CD 13 00 E1 18 F5
R 00 00 00 00 00 0A 00 00
T 42 00 00 00
R 00 00 00 00
T 42 00 00 00 F5 FD 21 00 00 FD 39 FD 36 00 00 2E
R 00 00 00 00
T 4E 00 00 00 0F 3E 42 CD 00 00 2E 00 3E 40 CD
R 00 00 00 00 02 08 03 00
T 59 00 00 00 00 00 CD 00 00 21 CA 00 CD
R 00 00 00 00 02 04 03 00 00 07 00 00 00 0A 00 00
T 62 00 00 00 37 00 FD 21 01 00 FD 39 FD 36 00 00
R 00 00 00 00 00 04 00 00
T 6E 00 00 00
R 00 00 00 00
T 6E 00 00 00 CD 0E 00 21 00 00 39 CD 22 00 B7 28
R 00 00 00 00 00 05 00 00 00 0C 00 00
T 7A 00 00 00 2A FD 21 00 00 FD 39 FD 6E 00 3E 40
R 00 00 00 00
T 86 00 00 00 CD 00 00 21 00 00 39 7E CD 13 00 21
R 00 00 00 00 02 05 03 00 00 0D 00 00
T 92 00 00 00 00 00 39 7E D6 0D 20 05 3E 0A CD
R 00 00 00 00
T 9D 00 00 00 13 00
R 00 00 00 00 00 04 00 00
T 9F 00 00 00
R 00 00 00 00
T 9F 00 00 00 21 32 00 CD 00 00
R 00 00 00 00 02 08 02 00
T A5 00 00 00
R 00 00 00 00
T A5 00 00 00 21 01 00 39 7E E6 07 C6 30 CD 13 00
R 00 00 00 00 00 0E 00 00
T B1 00 00 00 21 E1 00 CD 37 00 FD 21 01 00 FD 39
R 00 00 00 00 00 05 00 00 00 08 00 00
T BD 00 00 00 FD 34 00 21 FA 00 CD 00 00 18 A6 F1
R 00 00 00 00 02 0B 02 00
T C9 00 00 00 C9
R 00 00 00 00
T CA 00 00 00
R 00 00 00 00
T CA 00 00 00 41 43 49 41 20 36 38 35 30 20 74 65
R 00 00 00 00
T D6 00 00 00 73 74 20 72 65 61 64 79 0D 0A 00
R 00 00 00 00
T E1 00 00 00
R 00 00 00 00
T E1 00 00 00 0D 0A 00
R 00 00 00 00

36
build/main.sym Normal file
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@@ -0,0 +1,36 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next / eZ80 / R800) Page 1
Hexadecimal [32-Bits]
Symbol Table
.__.$$$. = 00002710 L
.__.ABS. = 00000000 G
.__.CPU. = 00000000 L
.__.H$L. = 00000000 L
0 ___str_0 000000CA R
0 ___str_1 000000E1 R
0 _acia_getc_nonblocking 00000022 R
0 _acia_init 00000000 R
0 _acia_putc 00000013 R
0 _acia_puts 00000037 R
0 _acia_status 0000000E R
_delay_ms ******** GX
_io_in ******** GX
_io_out ******** GX
0 _main 00000042 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next / eZ80 / R800) Page 2
Hexadecimal [32-Bits]
Area Table
0 _CODE size E4 flags 0
1 _DATA size 0 flags 0
2 _INITIALIZED size 0 flags 0
3 _DABS size 0 flags 8
4 _HOME size 0 flags 0
5 _GSINIT size 0 flags 0
6 _GSFINAL size 0 flags 0
7 _INITIALIZER size 0 flags 0
8 _CABS size 0 flags 8

BIN
build/out.bin Normal file
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Binary file not shown.

19
build/out.ihx Normal file
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@@ -0,0 +1,19 @@
:03000000C38001B9
:02000800ED4DBC
:02001000ED4DB4
:02001800ED4DAC
:02002000ED4DA4
:02002800ED4D9C
:02003000ED4D94
:02003800ED4D8C
:20018000F331FFFFCD8C01CDDE0018FE01000078B12808110080210080EDB001000078B1CF
:0E01A000280B210080AF77230B78B120F9C91E
:200080004F7DED79C94FED78C97CB5C8E52114002B7CB520FBE12B7CB520F1C92E033E20B8
:2000A000CD80002E153E20C380003E20C385006FE5CDAA00E1CB4F28F73E21C38000E5CD30
:2000C000AA00E10F3802AFC9E53E21CD8500E1773E01C97EB7C823E5CDAF00E118F5F5FD7D
:2000E000210000FD39FD3600002E0F3E42CD80002E003E40CD8000CD9C00216601CDD300E2
:20010000FD210100FD39FD360000CDAA0021000039CDBE00B7282AFD210000FD39FD6E0033
:200120003E40CD8000210000397ECDAF00210000397ED60D20053E0ACDAF00213200CD8953
:2001400000210100397EE607C630CDAF00217D01CDD300FD210100FD39FD340021FA00CDBA
:20016000890018A6F1C941434941203638353020746573742072656164790D0A000D0A003A
:00000001FF

11
build/out.lk Normal file
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@@ -0,0 +1,11 @@
-mjwx
-i build/out.ihx
-b _CODE = 0x0080
-b _DATA = 0x8000
-k /usr/sbin/../share/sdcc/lib/z80
-k /usr/share/sdcc/lib/z80
-l z80
build/boot.rel
build/main.rel
-e

175
build/out.map Normal file
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@@ -0,0 +1,175 @@
ASxxxx Linker V03.00/V05.40 + sdld, page 1.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000000 .__.ABS. main
00000000 l__CABS
00000000 l__DABS
00000000 l__DATA
00000000 l__INITIALIZED
00000000 l__INITIALIZER
00000000 l__ITABLE
00000000 s__CABS
00000000 s__DABS
00000000 s__ITABLE
00000000 s__ITABLE0
00000000 s__ITABLE1
00000000 s__ITABLE2
00000000 s__ITABLE3
00000000 s__ITABLE4
00000000 s__ITABLE5
00000000 s__ITABLE6
00000000 s__ITABLE7
00000001 l__GSFINAL
00000002 l__ITABLE1
00000002 l__ITABLE2
00000002 l__ITABLE3
00000002 l__ITABLE4
00000002 l__ITABLE5
00000002 l__ITABLE6
00000002 l__ITABLE7
00000003 l__ITABLE0
0000000C l__HOME
00000021 l__GSINIT
00000080 s__CODE
00000100 l__CODE
00000180 s__HOME
0000018C s__GSINIT
000001AD s__GSFINAL
00008000 s__DATA
00008000 s__INITIALIZED
00008000 s__INITIALIZER
ASxxxx Linker V03.00/V05.40 + sdld, page 2.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_CODE 00000080 00000100 = 256. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000080 _io_out
00000085 _io_in
00000089 _delay_ms
000000DE _main main
ASxxxx Linker V03.00/V05.40 + sdld, page 3.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE0 00000000 00000003 = 3. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 4.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE1 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 5.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE2 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 6.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE3 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 7.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE4 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 8.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE5 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 9.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE6 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 10.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_ITABLE7 00000000 00000002 = 2. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 11.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_HOME 00000180 0000000C = 12. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 12.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSINIT 0000018C 00000021 = 33. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 13.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSFINAL 000001AD 00000001 = 1. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 14.
Files Linked [ module(s) ]
build/boot.rel [ ]
build/main.rel [ main ]
ASxxxx Linker V03.00/V05.40 + sdld, page 15.
User Base Address Definitions
_CODE = 0x0080
_DATA = 0x8000

42
build/out.noi Normal file
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@@ -0,0 +1,42 @@
DEF .__.ABS. 0x0
DEF l__CABS 0x0
DEF l__DABS 0x0
DEF l__DATA 0x0
DEF l__INITIALIZED 0x0
DEF l__INITIALIZER 0x0
DEF l__ITABLE 0x0
DEF s__CABS 0x0
DEF s__DABS 0x0
DEF s__ITABLE 0x0
DEF s__ITABLE0 0x0
DEF s__ITABLE1 0x0
DEF s__ITABLE2 0x0
DEF s__ITABLE3 0x0
DEF s__ITABLE4 0x0
DEF s__ITABLE5 0x0
DEF s__ITABLE6 0x0
DEF s__ITABLE7 0x0
DEF l__GSFINAL 0x1
DEF l__ITABLE1 0x2
DEF l__ITABLE2 0x2
DEF l__ITABLE3 0x2
DEF l__ITABLE4 0x2
DEF l__ITABLE5 0x2
DEF l__ITABLE6 0x2
DEF l__ITABLE7 0x2
DEF l__ITABLE0 0x3
DEF l__HOME 0xC
DEF l__GSINIT 0x21
DEF s__CODE 0x80
DEF l__CODE 0x100
DEF s__HOME 0x180
DEF s__GSINIT 0x18C
DEF s__GSFINAL 0x1AD
DEF s__DATA 0x8000
DEF s__INITIALIZED 0x8000
DEF s__INITIALIZER 0x8000
DEF _io_out 0x80
DEF _io_in 0x85
DEF _delay_ms 0x89
DEF _main 0xDE
LOAD build/out.ihx

82
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@@ -0,0 +1,82 @@
#include "boot.h"
/*
* 6850 ACIA test wiring assumption:
* /CS2 is driven by not-A5, so the ACIA is selected when A5 = 1.
* RS is assumed to be wired to A0, giving:
* 0x20 = status/control
* 0x21 = data
*/
#define ACIA_CTRL_STATUS 0x20
#define ACIA_DATA 0x21
#define ACIA_STATUS_RDRF 0x01
#define ACIA_STATUS_TDRE 0x02
#define ACIA_CMD_MASTER_RESET 0x03
#define ACIA_CMD_8N1_DIV16 0x15
static void acia_init(void)
{
io_out(ACIA_CTRL_STATUS, ACIA_CMD_MASTER_RESET);
io_out(ACIA_CTRL_STATUS, ACIA_CMD_8N1_DIV16);
}
static uint8_t acia_status(void)
{
return io_in(ACIA_CTRL_STATUS);
}
static void acia_putc(uint8_t value)
{
while ((acia_status() & ACIA_STATUS_TDRE) == 0) {
}
io_out(ACIA_DATA, value);
}
static uint8_t acia_getc_nonblocking(uint8_t *value)
{
if ((acia_status() & ACIA_STATUS_RDRF) == 0) {
return 0;
}
*value = io_in(ACIA_DATA);
return 1;
}
static void acia_puts(const char *text)
{
while (*text) {
acia_putc((uint8_t)*text++);
}
}
void main(void)
{
uint8_t cnt = 0;
uint8_t ch = 0;
io_out(PIO_A_CTRL, 0x0F);
io_out(PIO_A_DATA, 0x00);
acia_init();
acia_puts("ACIA 6850 test ready\r\n");
for (;;) {
uint8_t status = acia_status();
if (acia_getc_nonblocking(&ch)) {
io_out(PIO_A_DATA, ch);
acia_putc(ch);
if (ch == '\r') {
acia_putc('\n');
}
delay_ms(50);
}
acia_putc((uint8_t)('0' + (cnt & 0x07)));
acia_puts("\r\n");
cnt++;
delay_ms(250);
}
}

6
test.lk Normal file
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@@ -0,0 +1,6 @@
-m
-i
-b _ITABLE = 0x0000
-b _CODE = 0x0080
build/out
build/test.rel